xilinx-suite
- Repo stars 287
- Author updated Live
- Author repo xilinx-skill
- Domain
- Other
- Compatible agents
-
- Claude Code
- Cursor
- Cline
- Codex
- Windsurf
- Gemini CLI
- +20
- Trust score
- 88 / 100 · community maintained
- Author / version / license
- @QingquanYao · no license declared
- Token usage
- Lean
- Setup complexity
- Guided setup
- External API key
- Not required
- Operating systems
- Linux
- Runtime requirements
- Python
- Permissions
-
- Read-only
- Write / modify
- Shell exec
- Network behavior
- Local-only
- Install commands
- 26 variants
Profile is derived at build time from SKILL.md and install vectors. Subject to drift from author intent.
Heads up: 未限定 allowed-tools,默认拥有全部工具权限。
---
name: xilinx-suite
description: > 本 skill 帮助你完成 Xilinx(AMD)完整设计流程,生成可直接运行的脚本和文件。 [可选] Vitis HLS → Vivado → Vitis Unified / PetaL…
category: other
runtime: Python
---
# xilinx-suite output preview
## PART A: Task fit
- Use case: > 本 skill 帮助你完成 Xilinx(AMD)完整设计流程,生成可直接运行的脚本和文件。 [可选] Vitis HLS → Vivado → Vitis Unified / PetaLinux C/C++ 算法 → IP 核 硬件平台设计 软件开发 / Linux 系统 hlsguide.md vivadoguide.md vitisunifiedguide.md runs entirely locally; runs on Python. Works with Claude Code, Cursor, Cline and 23 more..
- Inputs: target material, constraints, expected output, and acceptance criteria.
- Evidence boundary: follow “第一步:判断工具和流程 / 完整设计流程总览 / 工具路由表” and do not present inference as author intent.
## PART B: Execution result
- **01** The card summarizes the use case; runtime output centers on “> 本 skill 帮助你完成 Xilinx(AMD)完整设计流程,生成可直接运行的脚本和文件。 [可选] Vitis HLS → Vivado → Vitis Unified / PetaLinux C/C++ 算法 → IP 核 硬件平台设计 软件开发 / Linux 系统 hlsguide.md vivadoguide.md vitisunifiedguide.md runs entirely locally; runs on Python. Works with Claude Code, Cursor, Cline and 23 more.”.
- **02** When the source has headings, the agent prioritizes “第一步:判断工具和流程 / 完整设计流程总览 / 工具路由表” so the result follows the author’s structure.
- **03** Typical output includes task judgment, concrete steps, required commands or file edits, validation, and follow-up options.
- **04** Risk context follows the fingerprint: read files, write/modify files, run shell commands; mostly runs locally; usually needs no extra API key.
## Running Rules
- read files, write/modify files, run shell commands; mostly runs locally; usually needs no extra API key.
- Validate with a small sample before expanding scope.
- Return the result, validation criteria, and next iteration options. The source does not require a stable slash command. After installation, invoke the skill by name and describe the task.
Name target files or source material, expected output, forbidden changes, and whether network or shell access is allowed. Permission fingerprint: read files, write/modify files, run shell commands.
Start with a small task and check whether the result follows “第一步:判断工具和流程 / 完整设计流程总览 / 工具路由表”. Inspect diffs, logs, previews, or tests before expanding scope.
Confirm the final output includes a concrete result, evidence, and next action. If it stays generic, tighten inputs, boundaries, and acceptance criteria.
---
name: xilinx-suite
description: > 本 skill 帮助你完成 Xilinx(AMD)完整设计流程,生成可直接运行的脚本和文件。 [可选] Vitis HLS → Vivado → Vitis Unified / PetaL…
category: other
source: QingquanYao/xilinx-skill
---
# xilinx-suite
## When to use
- > 本 skill 帮助你完成 Xilinx(AMD)完整设计流程,生成可直接运行的脚本和文件。 [可选] Vitis HLS → Vivado → Vitis Unified / PetaLinux C/C++ 算法 → IP 核 硬…
- Use it when the task has clear inputs, repeatable steps, and validation criteria.
## What to provide
- Target material, scope, expected result, and forbidden changes.
- Whether network, commands, file writes, or external services are allowed.
## Execution rules
- Organize steps around “第一步:判断工具和流程 / 完整设计流程总览 / 工具路由表” and keep inference separate from source facts.
- read files, write/modify files, run shell commands; mostly runs locally; usually needs no extra API key.
- Validate with a small sample before expanding the task.
## Output requirements
- Return the deliverable, key evidence, validation method, and next action.
- Mark missing information as unknown; do not invent commands, platforms, or dependencies. The author source anchors workflow facts; repository files anchor sources and commands; Fluxly only adds fit, limitations, and quality judgment.
skill "xilinx-suite" {
input -> user goal + target files + boundaries + acceptance criteria
context -> 第一步:判断工具和流程 / 完整设计流程总览 / 工具路由表
rules -> SKILL.md triggers / order / output contract
runtime -> Python | read files, write/modify files, run shell commands | mostly runs locally
guardrails -> usually needs no extra API key + small-sample validation + diff/log review
output -> copyable result + checklist + next iteration
} Xilinx 全工具链 Skill
本 skill 帮助你完成 Xilinx(AMD)完整设计流程,生成可直接运行的脚本和文件。
第一步:判断工具和流程
收到任何 Xilinx 相关请求时,首先确定用户处于哪个阶段,然后加载对应参考文件。
完整设计流程总览
[可选] Vitis HLS → Vivado → Vitis Unified / PetaLinux
C/C++ 算法 → IP 核 硬件平台设计 软件开发 / Linux 系统
hls_guide.md vivado_guide.md vitis_unified_guide.md
+ mpsoc_ps_config.md petalinux_guide.md
+ xdc_constraints.md
工具路由表
| 用户描述的任务 | 需要的工具 | 加载的参考文件 |
|---|---|---|
| C/C++ 算法加速、pragma 优化、生成 IP | Vitis HLS | ../../references/hls_guide.md |
| 创建工程、Block Design、配置 PS/IP、XDC、比特流 | Vivado | ../../references/vivado_guide.md + 按需加载 |
| PS 详细配置(DDR、MIO、时钟) | Vivado | ../../references/mpsoc_ps_config.md |
| IO 引脚约束、时序约束 | Vivado | ../../references/xdc_constraints.md |
| JESD204B→C 迁移、高速串行 ADC/DAC 接口 | Vivado | ../../references/jesd204b_to_c_migration.md |
| 嵌入式软件、裸机程序、RTOS、platform/domain | Vitis Unified | ../../references/vitis_unified_guide.md |
| 嵌入式 Linux、kernel 配置、rootfs、启动镜像 | PetaLinux | ../../references/petalinux_guide.md |
| PetaLinux 上跑 gRPC C++ 服务端 / Python 客户端、ZMQ→gRPC 迁移、udmabuf+AXI DMA 暴露 RPC | PetaLinux | ../../references/grpc_on_petalinux.md |
| 查找官方文档编号、UG/PG/DS 编号查询、文档用途说明 | 通用 | ../../references/official-docs/index.md |
第二步:需求确认(必须先做)
在生成任何脚本之前,确认以下信息(没有明确答案的项主动提问):
所有工程必须确认
- 目标器件/开发板:完整 part number 或板型(由用户提供)
- Vivado/Vitis 版本(如 2023.2、2024.1)
- 设计目标:这个工程要实现什么功能?
HLS 工程额外确认
- 算法描述:C/C++ 函数的输入输出和功能
- 性能目标:目标时钟频率、延迟、吞吐量要求
- 接口类型:AXI4-Lite(控制)、AXI4-Stream(数据)、AXI4-Master(存储器访问)
Vivado 工程额外确认(MPSoC 类)
- PS 配置:DDR 类型和容量、MIO 外设(UART、Ethernet、USB、SD 等)
- PL IP 需求:需要哪些 AXI IP,是否有自定义 HDL 模块
- 时钟要求:PL 时钟频率(pl0_ref_clk)
Vitis 工程额外确认
- 运行环境:裸机(standalone)、FreeRTOS、还是 Linux 用户态
- 处理器核:A53、R5、MicroBlaze
- XSA 文件路径:从 Vivado 导出的硬件描述文件
PetaLinux 工程额外确认
- BSP 或 XSA:是否有厂商 BSP?或者直接使用 Vivado 导出的 XSA?
- 自定义需求:是否需要添加驱动/应用程序/设备树覆盖
第三步:按工具流程执行
确认需求后,加载对应参考文件并按步骤生成脚本。
加载参考文件的时机
始终在生成脚本之前先读取参考文件,不要凭记忆生成 Tcl/XSCT/命令,因为不同 Vivado/Vitis 版本的 API 有差异。
Vivado 工程 → 先读 ../../references/vivado_guide.md
→ 如有 PS → 再读 ../../references/mpsoc_ps_config.md
→ 如有 IO → 再读 ../../references/xdc_constraints.md
→ 如有 JESD204 → 再读 ../../references/jesd204b_to_c_migration.md
HLS 工程 → 先读 ../../references/hls_guide.md
Vitis 工程 → 先读 ../../references/vitis_unified_guide.md
PetaLinux → 先读 ../../references/petalinux_guide.md
→ 如需 gRPC(C++ server / Python client、ZMQ 迁移)→ 再读 ../../references/grpc_on_petalinux.md
输出规范
每次生成脚本时,必须提供:
- 完整可运行的脚本文件(
.tcl、.xdc、.py、shell 脚本等) - 运行命令:如何在命令行或 GUI 中执行
- 预期输出:脚本运行成功后会产生哪些文件
- 下一步提示:完成本阶段后应该做什么
文件组织规范
project_root/
├── 01_hls/ ← Vitis HLS 工程(可选)
│ ├── hls_create.tcl
│ └── src/*.cpp / *.h
│
├── 02_vivado/ ← Vivado 硬件工程
│ ├── create_project.tcl
│ ├── create_bd.tcl
│ ├── add_sources.tcl
│ ├── constraints/design.xdc
│ ├── build.tcl
│ └── output/
│ ├── design.bit
│ └── design_fixed.xsa
│
├── 03_vitis/ ← Vitis 软件工程
│ ├── create_platform.tcl (XSCT 脚本)
│ ├── create_app.tcl
│ └── src/*.c / *.h
│
└── 04_petalinux/ ← PetaLinux(可选)
├── build.sh
└── config/
跨工具数据流
Vitis HLS Vivado Vitis / PetaLinux
─────────────────────────────────────────────────────────────────────────
hls_ip/ → IP Catalog
solution/impl/ip → (add_files / ip_repo)
↓
project.xsa → 平台/BSP/Linux BSP
design.bit → boot/BOOT.BIN
常见错误和注意事项
- 版本兼容性:Vivado 2022.x+ 的
write_hw_platform替代了旧版write_sysdef;Vitis Unified 2022.x+ 的 Tcl API 与 Classic 版本有重大差异 - XSA 类型:
write_hw_platform(综合前,可编辑)vswrite_hw_platform -fixed -include_bit(实现后,固定含比特流) - HLS IP 导入 Vivado:需要在 Vivado 工程中添加 HLS IP 仓库路径,并刷新 IP 目录
- PetaLinux 版本匹配:PetaLinux 版本必须与 Vivado 版本一致(例如都用 2023.2)
- 器件系列判断:
zu开头 → MPSoC;vu/ku/xc7→ 纯 FPGA;xcvc→ Versal
参考文件
../../references/vivado_guide.md:Vivado 工程创建、Block Design、综合实现、报告分析../../references/mpsoc_ps_config.md:Zynq UltraScale+ PS 详细配置(DDR、MIO、时钟参数)../../references/xdc_constraints.md:XDC 约束完整指南(时序、IO、例外约束)../../references/hls_guide.md:Vitis HLS 工程流程(C/C++ → IP)../../references/vitis_unified_guide.md:Vitis Unified IDE 2022.x+ 工程流程../../references/petalinux_guide.md:PetaLinux 系统构建流程../../references/jesd204b_to_c_migration.md:JESD204B→C IP 迁移指南(端口映射、数据位宽、AXI 寄存器、常见陷阱)../../references/grpc_on_petalinux.md:PetaLinux + gRPC 端到端部署指南(rootfs 配置、libutf8_range 软链、VM 预生成 .pb.cc + 板上 g++、udmabuf/AXI DMA RPC 暴露、ZMQ→gRPC 迁移、常见 RCU stall 等陷阱)../../references/official-docs/index.md:Xilinx/AMD 官方文档索引(UG/PG/DS/XAPP 编号、标题、用途、与本仓库参考指南的对应关系)
Decide Fit First
Design Intent
How To Use It
Boundaries And Review